Many components and peripheral devices of both desktop and portable personal computers consume a great deal of power even when they are not active. For this reason, power management systems have been developed which cause each component or peripheral device to operate in the lowest power consumption mode with respect to present demands thereon. One basic type of power management system commonly implemented on portable computers monitors various peripheral devices for I/O activity. After a predetermined period of I/O inactivity, the computer is "powered down", i.e., the system clock is halted and power is removed from the hard disk drive, the floppy disk drive, the liquid crystal display (LCD), and miscellaneous system circuitry, thereby effecting more efficient use of remaining battery power.
More recently, improvements in the basic power management system have been introduced which include options such as blanking the liquid crystal display (LCD) or monitor screen after a predetermined period of I/O inactivity or turning off the hard disk drive motor after the hard disk drive has not been accessed for a predetermined period of time. Furthermore, there may be provided more than one reduced power consumption mode. For example, there may be a "stand by" mode in which certain components, such as the LCD and the hard disk drive motor, are caused to operate in a reduced power consumption mode but the processing speed of the central processing unit (CPU) is not affected. In a "sleep" mode, nearly all of the functions of the computer are slowed or halted, including the CPU. From the standpoint of power consumption, the sleep mode is substantially equivalent to turning the computer off, except that no data is lost.
One area of power management that has not been heretofore addressed involves the random access memory (RAM) subsystem of a computer. In some computers, the RAM subsystem comprises dynamic RAM (DRAM) chips, which are composed of an array of memory cells each comprising a transistor network and an intrinsic capacitor. In operation, the transistor network charges or discharges the capacitor, depending on whether a "1" or a "0" is to be stored in the cell. It is well known that, in order to maintain the integrity of the data stored in the DRAM cells, the cells must be periodically refreshed. Such refreshing may be accomplished by reading each row of the DRAM array into sense amplifiers in the DRAM and then writing the data back into the row, a process commonly referred to as a "row-only refresh". Refreshing an entire DRAM subsystem consumes a large amount of power. For example, a single Toshiba 1 Mb.times.4 DRAM chip requires an average refresh current of 1.04 ma. Because a RAM subsystem will most likely include more than one such DRAM chip, the total power consumed by the subsystem during refresh will be substantially greater.
Alternatively, the RAM subsystem may comprise static RAM (SRAM) chips. Unlike DRAM cells, SRAM cells need not be periodically refreshed; however, SRAM cells must be constantly energized in order to retain data stored therein. As a result, the use of an SRAM subsystem gives rise to power consumption concerns similar to those discussed in connection with DRAM subsystems.
Typically, a computer system will include enough RAM to accommodate the largest applications program that is expected to be executed by the computer. Therefore, during the execution of most programs, a substantial portion of the subsystem will not be in use, i.e., will not contain valid data. Ideally, then, in order to reduce unnecessary power consumption, this portion of the subsystem should not be energized (in the case of SRAM) or refreshed (in the case of DRAM). However, while it is presently possible to energize or refresh only certain individual RAM chips, rather than the entire RAM subsystem, it has not been possible to energize or refresh only a portion of an individual RAM chip, i.e., only that portion that contains valid data and therefore needs to be energized or refreshed in order to maintain the integrity of that data.
In general, during normal operation of a computer each RAM chip will contain some valid data. This effectively eliminates the option of energizing or refreshing only particular chips, as all of them contain valid data and must be refreshed. As a result, a substantial amount of power is wasted superfluously energizing or refreshing memory cells within each chip that do not contain valid data, thereby limiting the total amount of RAM which, due to power management concerns, may be optimally included in a computer's RAM subsystem. A method of power management applicable to RAM subsystems would be especially beneficial in connection with computer devices such as Personal Digital Assistants (PDAs), which, because they have no means for attaching external memory storage devices, such as a disk drive, require a significant amount of internal memory storage and which, because they are battery powered, have significant power management concerns.
Therefore, what is needed is a method of power management applicable to a RAM subsystem of a computer that enables the subsystem to operate in at least one reduced power consumption mode, in which only that portion of the subsystem that contains valid data is energized or refreshed.